highspeed electronic microcircuitry transmission-switching

Background reference:

While modern supercomputers target to afford the maximum computation power for electronic consumption power, even slowering the process speed as greaterly reduces the power consumption, their observable being consumption, remaining high but optimal,- yet their equation lacks a driver: the market is their driver.... A better optimization is to afford maximal computation power for waste, power; reducing waste power at the expense of some computational speed but thus allowing maximal packing, possibly even on molecular scale recovering speed by sheer minusculity ... the driver becomes feasibility, -of extremely-dense chunk-chips,- in lieu of markets. (*)

* (NB. The market, -in common economics,- tends to allow wastage as runoff; which would impose non-optimal design-methodology on microscale-fabricated processes running in the "whatever's-possible" scheme of cosmic-nature utilizing such wastage .... Ultimately, microcellular processors will be constructed by nanoscale-massproduction engineering, and wastage-engineering will be repackaged.)

But wastage was never intrinsic to the logical equation, but extrinsic, hors d'oeuvres still in the boxy implementation, to be eliminated from and for faster, boxes ... If the basic quantum of information signaling can be kept as a soliton, it may need not be wasted.

The fastest-coolest, contest of the late 1900's favored Schottky-damped (nonsaturating) TTL; But even at low-power, Schottky LSI large scale integration was hot, as the mode of TTL was hot: It dropped a significant current through a significant voltage, generating significant "you-know-wattage" mostly as heat not IR-photons, though hole-electron recombinatorics generates photons, because much of it was spent on field-acceleration of the majority carriers, electrons or holes ... digital-switching was alot cooler than linear-analog devicing, but at maximum speeds switching pushed into its analog-device characteristics and began heating without gaining more speed.

The coolest logic was in the NMOS/PMOS/CMOS category, requiring only high-impedance voltages to switch currents and whence voltages across more-of-the-same resistors, which being very-high, the wattage was very low, but so was the RC-coefficient slower.

The fastest logic was the ECL emitter-coupled logic, also referred-to as, current-mode, (as distinct from voltage-mode, TTL, CMOS, I²L integrated-injection-logic), but it poured current down the drain (or rather down the "bipolar emitter" doing the draining) while operating at similar voltage, whence much greater wattage, and much-less, packing.

(I did not read of specific FET-D-'CL logic production, though it seemed feasible into a high-resistance-load common "drain",- But it would have mixed the two very-unlike modes, with little to gain: ECL itself already had very good fanout, ratio; and much of the early work in packing for smaller circuits focused on simplifying transistor-fanning structures without invoking diac/triac/SCR-latch-on.)

If ECL could have been done at the quantum-current level, it might have recovered much wattage-wastage ... And this was the goal of cryogenic-superconductor-junction computers (and of much subsequent research into high-temperature superconductivity [*]).

Parallel-current switching:

But ECL, S-TTL, CMOS, were unipolar-signaling, whereas, the potentially least-wasteful, and equally-fast, -information, current,- would be afforded by quantum complementary parallel-current-mode transmission-line logic,- which basically never, stops, currents (never instantly generates high voltages) and so never radiates broadside RF energy ... What voltage it uses, travels near lightspeed, and its information content is in its digital polarity, left-line-or-right ... much like photon-computing but in the EHF mm-range.

Transmission lines operate at typically 60% lightspeed (1.6 index-of-refraction), whereas semiconductor nonballistic electron and hole mobility velocity has been limited around 107cm/sec. ~ 0.03% lightspeed, limiting the carrier rates within gates. By using transmission-switching of current, we should achieve a thousandfold improvement in signal-logic (*), or a hundredfold over the contemporary, HEMT.

* (off-topically, a portion of an electromagnetic wave may exist preceding its lobe wave in transmission media, -and maybe in lightly implanted and shallow-implanted semiconductor substrates too,- not unlike the unequal speeds in birefringence, but being in-polarity, the preceder may be only statistically important to the receiver, the actual photon arriving later, in early-triggering metastable and exclusionary events, left-right selection of molecular bonding sites, coupling of electron orbitals, increasing radiodecay; or adding to the overall aether-chop on the stellar scale.)

Charge-splitting on flat-conductors:

We propose to implement ballistic-electron current parallel-routing and switches as signal-lines of constant-current diverted minutely as-if left-conductor or-right, for "EHF-photon" signals. (And, maybe things as current-recovery by full-wave ballistic-rectification.)

The basic signal line in semiconductor microcircuitry may utilize the micro-parallel doubly-stepped-workfunction, an application of that technology presently used to speed-up the HEM(FE)T a thousandfold;- The basic control gate being a localized line-widening to increase its voltage by increasing its impedance and slow its current to be applied about an interstitially-passing controlled-line ...

To minimize RF radiation, the gate may be bounded within a mirror, or the lines may be wound together in a short helical cycle (a 3-D circuit) to cancel the radiation.

Notes on substrate impression:

Semiconductor circuit-layout at ballistic-electron speeds is fluid-(plasma)-dynamic: the electrons scatter on the substrate atomic-nuclei protons, -and on other electrons;- the usable signals (intended) are short solitons (pseudo-wavicle), dimensionally a few million atomic-radii wavelength ... The conductor channels are designed to maintain soliton-shape: channel-edges are graded, turns are gentle and asymmetrically graded, and channel-widths are modulated to adjust speed-switching clarity.

The circuits are packed in 1-10µm layers on a single chunk-chip, thousands per centimeter grown epitaxially, and signals fed between layers by bit-poles rather than coalesced onto backplanes (but similarly nevertheless); a teraflop in an oversized cufflink.

[under further construction]

Simply-failed layers may be switched-out, powered-off.

* [A note on the side: Look at superconduction by s-orbital-tunneling electron pairs along covalent-strings, either electron-deficient ("holes") or half-depleted: Work function orbitals should keep the electron pairs away from ionization, and, nuclear scattering ... the main obstacles are the consecutive orbital electrons taking their anti-spin reductions alternately, but the atomic-scale grating should still be fairly transparent to the tunneling electron pair,-- and mostly-filled electron-deficient (superconducting holes) might be the better choice as the pair would also take the anti-spin reduction and might contain that energy-split in continual exchange ... Also, the velocity involves a portion of 2/π-path-routing comparable to the index-of-refraction]

This article was updated partially in collaboration with a screenplay development.

Grand-Admiral Petry
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1998, 2005