gate-lines efficiency
|
digital binary (bit) electronic hardware bases 2 and 4, oft equally effectual,
aren't always most efficient for process |
This example is the multiplexor realestate in gate-lines:
The 1-of-2^N multiplexor decodes N address bits in AND-gates,
AND with the input bit, the one selected reaches the OR-stage and thence output.
If we model gates simply, there are input- and output-lines,
and the gate itself is tiny at the end of a line (and down in the practical substrate);
... but the stage delays cut the overall utilization efficiency: Whence a tally:
- Base 2: (2/1) 2^N-(1/1) 2AND+(2OR/2) in N/1 stages:
approx. (4.000) 2^N AND-inputs; (2.000) 2^N AND-out-to-OR-inputs;
(1.000) 2^N OR-outputs; (1.000) N stages;
subtotal (5.000) 2^N; relative efficiency cost = 5.000 (external lines)
total (7.000) 2^N; relative efficiency cost = 7.000 (external+internal)
- Base 4: (4/3) 2^N-(1/3) 3AND+(4OR/4) in N/2 stages:
approx. (4.000) 2^N AND-inputs; (1.333) 2^N AND-out-to-OR-inputs;
(0.333) 2^N OR-outputs; (0.500) N stages;
subtotal (4.333) 2^N; relative efficiency cost = 2.167 (external lines)
total (5.667) 2^N; relative efficiency cost = 2.833 (external+internal)
- Base 8: (8/7) 2^N-(1/7) 4AND+(8OR/8) in N/3 stages:
approx. (4.571) 2^N AND-inputs; (1.143) 2^N AND-out-to-OR-inputs;
(0.143) 2^N OR-outputs; (0.333) N stages;
subtotal (4.714) 2^N; relative efficiency cost = 1.571 (external lines)
total (5.857) 2^N; relative efficiency cost = 1.952 (external+internal)
- Base 16: (16/15) 2^N-(1/15) 5AND+(16OR/16) in N/4 stages:
approx. (5.333) 2^N AND-inputs; (1.067) 2^N AND-out-to-OR-inputs;
(0.067) 2^N OR-outputs; (0.250) N stages;
subtotal (5.400) 2^N; relative efficiency cost = 1.350 (external lines)
total (6.467) 2^N; relative efficiency cost = 1.617 (external+internal)
- Base 32: (32/31) 2^N-(1/31) 6AND+(32OR/32) in N/5 stages:
approx. (6.194) 2^N AND-inputs; (1.032) 2^N AND-out-to-OR-inputs;
(0.032) 2^N OR-outputs; (0.200) N stages;
subtotal (6.226) 2^N; relative efficiency cost = 1.245 (external lines)
total (7.258) 2^N; relative efficiency cost = 1.452 (external+internal)
The general equation for approx. total realestate by base-radix R,
(R/R-1)((L2 R)+2+(1/R)) 2^N,
bottoms at (R-(Ln R) = 1+3Ln2), base R = 4.607; total = 5.647;
relative efficiency cost = 2.562 (external lines).
[under revision for a simpler in-practice model]
The TTL (cf 7400-series) NORAND consisted of AND-structure reverse-diode inputs to a
transistor amplifier, which output OR-structure summed into the final amplifier,
which had an inverting NOT-structure output. And most other gates in the entire line
consisted of one or more layers of NORANDs, eg. the AND-gate was a multiinput single-AND
single second-level NOR with an additional NORAND tied-down as a NOT-output ...
(so reminiscent of the ten-transistor imported radio of the 1960's:
that had three transistors actually connected and the third was tied-down as a diode) ...
the TTL NAND was therefore slower by that one extra NOT stage.
The multiplexor, was a significant high-tech use of the NORAND: it fully decoded address
bits; which required its AND-structure, and needed only one output answer, which was the
OR-sum of all the ANDs -only one selected per address-... its NOT-output being a choice.
Decoding the addresses, took 2 NORANDs per address bit, buffering the positive input and
generating a NOT-version (they usually did not change the TTL staging structure inside:
that came later in LSI, large scale integration, and generated Industry Alerts when all
the outputs twitched and drifted, despite its spec'd. power-ground-EMI caps. and changed
signal-set-up- and -fanout-timings); and an AND-structure for each of 2^N
unique addresses, including its data bit; and the NOR-structure output. The data input
AND-structure input for each of bits for any base, plus the base-number of bits to
decode the unique address; then a tree of condensing stages for multiplexing large
numbers of input bits, which stages took additional time-per, which factors-down the
hardward efficiency (cf large numbers of slow processors, are nominally equivalent to
fewer faster processors if the work is general and not special-case required instantly):
Tally: (N-bit address; 2^N data-bit-inputs)
- Base 2: 2^N(2/1)-(1/1) 2AND+(2NOR/2) in N/1 stages; approx. cost=
= 2^N(4.00) AND-diodes*; 2^N(2.00) AND-pullups* and
NOR-buffers*; 2^N(1.00) NOR-outputs*; N(1.00) stages;
= 2^N(20.0+3.0R)
- Base 4: 2^N(4/3)-(1/3) 3AND+(4NOR/4) in N/2 stages; approx. cost=
= 2^N(4.00) AND-diodes*; 2^N(1.33) AND-pullups* and
NOR-buffers*; 2^N(0.50) NOR-outputs*; N(0.50) stages;
= 2^N(13.7+1.8R)
- Base 8: 2^N(8/7)-(1/7) 4AND+(8NOR/8) in N/3 stages; approx. cost=
= 2^N(4.57) AND-diodes*; 2^N(1.14) AND-pullups* and
NOR-buffers*; 2^N(0.58) NOR-outputs*; N(0.33) stages;
= 2^N(13.8+1.7R)
- Base 16: 2^N(16/15)-(1/15) 5AND+(16NOR/16) in N/4 stages; approx. cost=
= 2^N(5.33) AND-diodes*; 2^N(1.07) AND-pullups* and
NOR-buffers*; 2^N(0.33) NOR-outputs*; N(0.25) stages;
= 2^N(12.7+1.4R)
- Base 32: 2^N(32/31)-(1/31) 6AND+(32NOR/32) in N/5 stages; approx. cost=
= 2^N(6.19) AND-diodes*; 2^N(1.03) AND-pullups* and
NOR-buffers*; 2^N(0.19) NOR-outputs*; N(0.20) stages;
= 2^N(12.5+1.2R)
* (1x AND-diodes were no-gain-transistor emitter E connections over a common base B)
* (Rx Standard pullups were resistive, and expensive in silicon realestate; and...)
* (1x efficiency used current-matching-transistors on a reference resistive; and...)
* (2x pulled-up a common [but no-gain] base B biased and no-gain collector C output)
* (3x NOR-buffers were a cascade-driver transistor)
* (6x NOR-outputs were two big transistors; and...)
* (Rx a small but expensive resistive pullup,- plus sometimes a resistive limiter)
(no-gain, meant, much less than unity, but could drain-off floating charge, for speedup)
Many attempts were made to make TTL more substrate-efficient: the "no-gain trick" allowed
adjacent inputs fairly closely spaced, without (NNN)PN- or (PPP)NP-crossleak, while fast
draining any floating charge: one of the major slowdowns in TTL. Schottky itself reduced
excess base (over)drive-charge by drawing-off through a low-voltage Schottky diode into
the collector. Low-power Schottky balanced TTL-similar speed at lower total power usage;
which also allowed for higher density LSI. Later follow-ons, Integrated Injection Logic
I2L, and Advanced CMOS-inside-TTL ACT, and Advanced cmos-inside-Schottky-TTL
AST attempted to further reduce power and increase speed ... these were commonly used in
V-LSI where internal speed was valued. And soon thereafter, VHDL and computer-on-a-chip
dominated the industry allotment for new-research, virtually squelching TTL advances.
[under construction]
© 1979, 2004
GrandAdmiralPetry@Lanthus.net