CMOS VLSI (contemporary improvements)

CMOS Complementary-Metal-Oxide-Semiconductor is frontrunner in industry VLSI/VHDL microcircuitry, but needs some fixes

[See also substrate notes]


Turning-on a CMOS-FET is fast: The applied Gate voltage, differential to either the Source or Drain, force-drifts minority-carriers from the nearby active pads (Source and Drain; n+/p+-doped), across, to diffuse under the Gate-insulation (SiO2), and so connects the circuit...

But, Turning-off the CMOS-FET is a little slower: Though not as saturable as bipolar, nevertheless minority-carriers under the Gate are a charge/current-ribbon (charge, when static; current, when dynamic, easily 50% duty-cycle) and, switching-off the Gate blows the ribbon away from the Gate, not all back into the Source and Drain but into the carrier well which is only lightly-doped and doesn't recombine immediately: the ribbon, despite being spread thin, still connects and some current must flow, even additionally via the carrier well bias, until the ribbon is cut; the broad pnp-like or npn-like FET structure is by design sub-unity-gain to help douse the current via the outer structure... The ribbon may also reach below the carrier well, into the intrinsic substrate.

An improvement may be to heavy-dope a sub-well-pad: which would be 'easiest' done in epitaxial fabrication, to lay down the sub-well-pad first, then 'grow' a thin epitaxial layer atop the substrate, for the main well and circuitry....


And-Series in compound-Gate-logic, either n/p-FET, is absolutely slow, and, relatively compared to the Or-Parallels in the same Gate-logic, because all-but-the-end FET's (grounded or powered) are isolated until all-nearer-the-end are turned-on, and even then, must wait on diffusion current, rather than fast drift current, to connect-across: like slowed-lightning, drift current can only turn-on an end FET, and that charge then diffuses, across the remainder of the equally-gated inline series: Series, is slow, even for very-closely-spaced multiple-Gates in contemporary circuit design: slow as diffusion....

So, to speed-up the series-FET-chain, to be as fast as parallel in which each FET is an end (grounded or powered), we must insert charge-primers to each isolated FET, capacitive-coupled active pads between FETS, over-gated as end-FET's, should do nicely, instead of contemporary closely-spaced diffusion Gate regions: Then, as each inline-isolated FET is turned-on by its Gate, it instantly draws a priming-charge -by drift current- from the nearest capacitive-active pads: so it's ready to run current as soon as all, in the series, are turned-on....


Where tri-state is necessary (though standard logic is preferred), the primary enable-signal delayed through a transfer-FET-pair both gated always On-- slows the signal to better match its signal-complement via an Inverter and so reduces crowbar-duty-cycle inherent in skewed-time enable-signal-pairs....

[under further construction]

Interline ringing crosstalk, suface effect aka 'skin' effect (deep pad mirroring), circuit flow directionality efficiency, multilayer, quad-layer latchup,...

This article was developed in part for a lab class.

A premise discovery under the title,

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