84 pin, 80 bit data, IC plan
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maximizing the bus-throughput
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Optimal computer partioning suggests that an IC that spews data
is the most efficient use of the backplane bus: remove extraneous
hand-wringing functions, and supply data, data-timing, and IC power.
Given that fair numeric precision has about 18 digits
~ 62 bits [being almost a power of 2],
and scale-range about ±9910 ~ ±3292
or 2 digits plus sign, or almost 10 bits -
~8210 is the mass of the cosmos in electrons ...
I suggest a data format consisting of
- 60 bits of precision with appended head and tail '1's
- 10 bits of scaling characteristic
- 10 bits of precision control
- generally 10-bit basic data-letters {indexes, integers}
Add power, ground and strobe: the 84 pin IC plan.
Each IC shall receive address control on strobe-high,
and transceive data on strobe-low.
A separate IC unit generates the strobe.
[A fancy master IC might detect and supply the lack of strobe]
84 pins:
- 1 power Vcc
- 1 ground Vgnd
- 1 strobe-in
- 1 enable-in
- 60 data bits
- 10 characteristic bits
- 6 data-precision bits [specifies the LSB position]
I/O input/output buffering to the bus is achievable by utilizing
half-bus IC's: 40 bits data to/from the bus, and 40 external.
[under construction]
© 1996 GrandAdmiralPetry@Lanthus.net