|minimizing the [IC pin-count] bus-throughput|
Optimal circuitry simplification suggests that an IC that streams serial data bits is the most efficient use of the pin-count - the extreme-ultimate is a zero-pin spheroidic IC conducting by contacting [informations traveling as spherical waves] through its shell-surface, combining and phase-chop/alternating: power, ground, two data-bit-streams, intrinsic-timing.
A variety of information/power extraction techniques are available:
More conveniently meanwhile [we] remove extraneous hand-wringing functions, and, stream dual-port one-bit data, data-timing and control, and IC power-and-ground, through six-pin IC's - six-face cubes fairly conveniently grid-locked in 3-space.
[from ca 1978]
The data shall consist of bit-streamed [variable-length blocked] low-order-bit-first phrases [limited only hereïn arbitrarily to 1024 bits total] - numbers beginning with the sign-bit, then scaler [binary-exponent] and fraction [precise value]. The CPU, the most complex IC, operates on pairs of bits, and streams addresses and data to all IC modules: Each IC responds upon self-recognizance: each contains its own self-addressing logic, multiple memory [1024bit] address-registers, and sequencers. I/O processors need only respond on one port - the other port being the external serial-data. . . . . . .