Tempest : Engineering Design

Notes on meeting Crypto-TEMPEST requirements in electronic equipment. (This is to be the basis of a course long due in our higher colleges of technology and science.)

technology is today;
government is yesterday;
science is tomorrow;
mathematics is now.


[See also: Engineering : Review]
  1. fully utilized ROM - no idle space
  2. secure 'back-up' routines - simpler functions, 'harder' crypto (separation)
  3. encrypted ROM source, run-time de-crypt-load-ed into DRAM (dynamic only)
  4. message redundancy reduction - (all) codes equally readable (if not actual) messages
  5. path-memory (history) at message level - network maintenance analysis
  6. restricted code-clock access - WOD-related entry-code, (3.6) minute code-free adjustment maximum
  7. hardware guide-rules
    1. reinput output, compare periodically
    2. vertical structure processor, multiply reutilized resources, resource checker
    3. memory parity (run-time), memory longitude-check (occasional)
    4. memory reallocation (periodic) to random [memory] address
    5. memory fallowing - dual/multi masked parities [data+address]
      reprogrammed upon each new load [of a memory-segment]
      [extensibly memory encryption, and some fewer parities]
    6. memory parity toggle (forced error: parity-test-testing)
    7. instruction code parity checkable [on direct-read]
    8. inter-box 'QTK' Quadrature-Transition-Keying (two-lines: 'one', 'zero')
        upgrade to shielded twisted Tri-Par (3-conductor counter/clockwise phase rotation 100-010-001, magnetically-coupled constant-current)
    9. inter-box 'PN' mask - resynchronized anachronously
  8. formal minimal interface:
    1. standardized Zoomath 16-key calculator numeric key-pad data/command
    2. standardized 26+2-key lingo-spell-numeric pad, spell-assist
    3. standardized 4 "live-music" control-cues
  9. hard-fail vrs. soft-fail - "top-of-hill" (always down-hill) early computer design
  10. preferred time-serial (vertical) architecture
    1. minimum hardware, minimal leak, maximal reuse
    2. reused functions all/none leak detectability everywhere
  11. failure detection and correction at the unit/module/sub-system level
    1. distance '2' coded addresses single-bit-failure stop
    2. parity check on all data sequences stops one-timers
    3. include parity check on both addresses and data together
    4. feedback from outputs data-checked or parity-checked
    5. periodic 'PN' check plus null and erasure checks
  12. failure history
    1. sub-system isolation/warning
  13. failure severity criteria
    1. [a-f] drop-out bits
    2. [a-] cross-over-tied bits
    3. [a-] cross-into-tied bits [leaving one output-disconnect]
    4. cross-outfrom-tied bits [leaving one input-disconnect]
    5. VCC-power and VGND range-check-tests
  14. isolation of data input and transmit ports/paths
    1. computed coded data-types/checks, cross-system watching
    2. security routine metric hardness summation or sub-unity check
    3. periodic memory/ph/unit/logic/... checks
  15. default values
    1. idle noise-sequences
    2. system self-interrogating/equipment-tallying

Grand-Admiral Petry
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