CMOS Complementary-Metal-Oxide-Semiconductor is frontrunner in industry VLSI/VHDL microcircuitry, but needs some fixes |
[See also substrate notes]
But, Turning-off the CMOS-FET is a little slower: Though not as saturable as bipolar, nevertheless minority-carriers under the Gate are a charge/current-ribbon (charge, when static; current, when dynamic, easily 50% duty-cycle) and, switching-off the Gate blows the ribbon away from the Gate, not all back into the Source and Drain but into the carrier well which is only lightly-doped and doesn't recombine immediately: the ribbon, despite being spread thin, still connects and some current must flow, even additionally via the carrier well bias, until the ribbon is cut; the broad pnp-like or npn-like FET structure is by design sub-unity-gain to help douse the current via the outer structure... The ribbon may also reach below the carrier well, into the intrinsic substrate.
An improvement may be to heavy-dope a sub-well-pad: which would be 'easiest' done in epitaxial fabrication, to lay down the sub-well-pad first, then 'grow' a thin epitaxial layer atop the substrate, for the main well and circuitry....
So, to speed-up the series-FET-chain, to be as fast as parallel in which each FET is an end (grounded or powered), we must insert charge-primers to each isolated FET, capacitive-coupled active pads between FETS, over-gated as end-FET's, should do nicely, instead of contemporary closely-spaced diffusion Gate regions: Then, as each inline-isolated FET is turned-on by its Gate, it instantly draws a priming-charge -by drift current- from the nearest capacitive-active pads: so it's ready to run current as soon as all, in the series, are turned-on....
[under further construction]
Interline ringing crosstalk, suface effect aka 'skin' effect (deep pad mirroring), circuit flow directionality efficiency, multilayer, quad-layer latchup,...
This article was developed in part for a lab class.
A premise discovery under the title,