| engineering at the LSI level should have had simpler FIFO's |
A communications-FIFO is an efficient LSI IC, a 20-pin 128x8 bit FIFO, 8-bits-in, 8-bits-out (3-state), strobe-in, strobe-out, Vcc, GND, that was not in the classic TTL IC manuals, by any of its parameters: It's different than the '70-80's-contemporary technology: It performs basic data functions in addition to simpler signal functions: It is not only a FIFO of good speed and size, width and length (the 8-bit path common among the fastest binary logic SSI, MSI, LSI, and early VLSI), it also condenses computational operations: applications where it is most used in research and development designs: It conveys its own status through its data path: It sends nulls when empty (as most standard FIFO's did) and erasures (rub-outs) when overflowing full: automatically inserting a long block to advise the receiving processor of its demise of data - this was the action that ordinary FIFO's did not: instead signaling on extra bit lines: which costs processor-style digital electronics more condition-testing, yet rarely occurring: The longer FIFO should never overflow in any case - whence such an eventuality should cost less of the regular processing time and program space. And as processor-style electronics tends to be efficient on wider 8-bits paths, the inclusion of status as control-data is paramount to effectual design technique.
The best C-FIFO testing, though, does entangle some time-synchronicity challenge: The best order for monitoring and responding to an overflow occurrence, requires watching ahead for such occasion, then releasing current data only after preinspection of the next control-data - lest the tail-end of the last data sequence partially truncate to erasures. With forwarding-looking the pre-detection of an erasured control-datum prevents utilization of the potentially truncated prior data: as that is generally undesirable in any computer processing: A false signal is frequently worse by being out-of-prescribable-range, than the absence of the next control all together, which can usually be delayed. And a pre-detected control-datum error, can be recovered in the full duplex mode: The receiving processor catches the incoming overflow, advising by sending a report-back on the return-data C-FIFO, and together these processors re-synchronize the C-FIFO path. If a return overflow spills the report datum, the similar report from the other side gets through, having already half-erasured-half-emptied the C-FIFO in its overflow: Together the two sides resolve to flush-clear the overflow and restore full duplex control-data synchronicity, with very brief process delay.
However much said for overflow detection, the likelihood is by design low enough that its occasion spells more than synchronization trouble: usually a malfunction or disfunction of either of the two processors - and reports should be sent by other route as well, that the hardware may be ordered to reset as a next resort in attempting line recovery: Third-way status-routing expands into multiprocessor cross-monitoring.
C-FIFO applications are generally in signal and small-data processing: I/OP sequencers, data-device drivers, inter-box control-data conduits: Each processor sends control+datum sequences comprised of a lead 8-bit control, which could be the null-zero no-datum singlet or the all-ones (hexdecimal FFx) erasure-status with design-optional datum follow-up, and its assigned-length datum [limited to 98% of erasure length] which completes a standard device+function+options+specifiers+values element outgoing, or device+purpose+options+status+specifiers+values incoming. [The control+datum sub-specification being thereunder designable]
The receiving process retrieves a presumed lead 8-bit control [after having initialized the pathway at power-up or reset to null-zeros] and parses it for subroutine direction: A null-zero is quickly avoided in the cycle, for its (typically) inefficient frequency, and the control branches to process the remainder and any subsequent length of datum: pulling-in presumed valid 8-bit datum fragments. In the rare occasion of an erasure the control-branching interpretation leads eventually to re-assume the C-FIFO's overflow, then stripping the subsequent stream of auto-imposed erasures till the first nonerasure - this could exceed the length of the C-FIFO if the source is send-bursting. Since neither processor has prior information regarding a C-FIFO overflow condition, the receiver must announce the discovery by report-back: either status such as an erasure-stream deliberately sent or (similarly) an overflow (forced) in the process of report-back, informs the other "sender" to recover the previously outgoing stream to a back-up check-point - that being a responsibility of both processors - resynchronize the C-FIFO, and resume sending from the check-point - without loss of control+data synchronicity, albeit a never-intended significant interstitial delay.
The datum can also include a segment-parity check (block or cyclic) - for example, a cumulative reverse-subtraction catches arithmetic errors similarly to a check-by-eleven, catching errantly inserted null-zeros (that alone are the exceptions).
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[NB: The remark for half-erasured+half-emptied may indicate a specific design intention not everywhere needed: allowing for causing overflow]
This concept was originally developed for a 1970's USAF SAC CP modem processor.