84 pin, 80 bit data, IC plan

maximizing the bus-throughput

Optimal computer partioning suggests that an IC that spews data is the most efficient use of the backplane bus: remove extraneous hand-wringing functions, and supply data, data-timing, and IC power.

Given that fair numeric precision has about 18 digits ~ 62 bits [being almost a power of 2], and scale-range about ±9910 ~ ±3292 or 2 digits plus sign, or almost 10 bits - ~8210 is the mass of the cosmos in electrons ... I suggest a data format consisting of

Add power, ground and strobe: the 84 pin IC plan. Each IC shall receive address control on strobe-high, and transceive data on strobe-low. A separate IC unit generates the strobe. [A fancy master IC might detect and supply the lack of strobe]

84 pins:

  1. 1 power Vcc
  2. 1 ground Vgnd
  3. 1 strobe-in
  4. 1 enable-in
  5. 60 data bits
  6. 10 characteristic bits
  7. 6 data-precision bits [specifies the LSB position]
I/O input/output buffering to the bus is achievable by utilizing half-bus IC's: 40 bits data to/from the bus, and 40 external.

[under construction]

Grand-Admiral Petry
'Majestic Service in a Solar System'
Nuclear Emergency Management

1996 GrandAdmiralPetry@Lanthus.net